IIT-G develops tech to design integrated circuits for efficient computing

Guwahati, May 11: A group of researchers at the Automation, Verification and Security Lab of Indian Institute of Technology-Guwahati (IIT-G) have developed a technology to design secure and dependable integrated circuits (ICs) for faster and efficient computing.

A statement from the institute informed here that the research has covered all aspects of the automated electronics design process such as synthesis, verification and security, which is aimed at strengthening the electronics manufacturing ecosystem.

The findings of the research have been published in top tier journals and conferences of the Institute of Electrical and Electronics Engineers (IEEE).

The paper has been authored by Chandan Karfa, associate professor, department of computer science and engineering, IIT-G and co-authored by his research students, Mohammed Abderehman, D. Senapati, Surajit Das, Priyanka Panigrahi and Nilotpola Sarma.

The team has collaborated with various international experts.

Pointing out the importance of research in the area of increasing computational power, Karfa said, “A promising technology to improve computational efficiency is hardware accelerators. In hardware acceleration, specific tasks can be offloaded to dedicated hardware instead of being performed by the CPU core of the system. For example, visualisation processes may be offloaded onto a graphics card, thereby freeing the CPU to perform other tasks.”

The research team is funded by ECR (Early Career Research), CRG (Core Research Grants) and Interdisciplinary Cyber-Physical Systems (ICPS) grants from the department of science and technology and by a research fellowship from Intel (India).

With increasing computational demands, there is a need for application-specific processors that can outperform current CPUs.

While multi-core processors are being used in modern times, their computing power improvements continue to be insufficient.

The IIT-G team emphasises on hardware acceleration specifications that are often written in high-level languages like in C/C++ and are converted to hardware code (or register transfer level or Register−Transfer Level (RTL code), in a process called High-Level Synthesis (HLS).

The team has developed simple and fast tools for HLS validation.

“We have developed two tools to validate the HLS process. One is FastSim, an RTL simulator that is 300 times faster than existing commercial simulators.  The other is DEEQ, which is an automated C to RTL equivalence checking tool for HLS verification. There is no other tool in the market with similar features,” Karfa said.

In addition to these simulators, prototypes of which are available for testing, the IIT-G team has also developed a technology called HOST, which protects Integrated Circuits from IP theft during the design cycle.

“The impact of the research team’s work is enormous because of the increasing demand for hardware accelerators in disruptive areas such as Internet-of-Things (IoT), embedded and cyber-physical systems, machine learning and image processing applications,” the statement said.



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